1. Field of the Invention
The present invention relates to a semiconductor device and more specifically to a semiconductor device of which noise resistivity is improved by utilizing a dummy field.
2. Description of the Background Art
With higher integration of semiconductor devices, elements such as transistors included in the semiconductor devices are miniaturized.
Conventionally, the LOCOS (Local Oxidation of Silicon) method was mainly used for isolating such elements as transistors. In recent years, trench isolation capable of attaining a narrower isolating region has been utilized. In trench isolation, a trench is formed at a main surface of a semiconductor substrate and the trench is filled with an insulating material to isolate elements.
In order to fill the trench with an insulating material, the insulating material is once deposited on the entire main surface of the semiconductor substrate after formation of the trench, and the insulating material is removed in a region where the trench was not formed. The most effective method of this kind is chemical mechanical polishing (hereinafter referred to as CMP).
When the trench width is large in the CMP process, however, the insulating layer is excessively etched at the center of the trench and dented in a dish shape. Thus, a "dishing phenomenon" is caused and precision in the form of the active region that is the region other than the isolating region is lowered.
In order to address this problem, a dummy pattern as a region where a trench is not formed is inserted in a region where the trench width is large. Hereinafter, a dummy active region formed by this dummy pattern is referred to as a dummy field.
FIG. 29 is a view for illustrating a dummy field.
In FIG. 29, a portion where an element isolation trench is not formed, that is, an active region and a dummy field are shown by oblique lines. FIG. 29 shows a region on the periphery of a pad 302 on a larger scale.
Referring to FIG. 29, a region 314 for forming transistors and the like is provided adjacent to pad 302. In region 314, guard rings 304, 306 are provided which are for supplying fixed potentials such as a power supply potential and a grand potential to a well where a transistor is formed. In guard rings 304, 306, regions 310 and 308 are provided on which gate electrodes are placed to form transistors.
A region 318 is an element isolating region in a portion other than region 314 and has at least a prescribed width. In region 318, dummy fields 312 are regularly provided at regular intervals to solve the above mentioned problem. Preferably, dummy fields having almost the same size as regions 308, 310 for forming transistors are regularly arranged at regular intervals, as shown in FIG. 29, to planarize the entire surface in the CMP process. However, a large dummy field may be provided in region 318.
FIG. 30 is a cross sectional view showing the cross section of a portion where a dummy field is formed.
Referring to FIG. 30, a P well 72 is formed in a P substrate 62, a trench for element isolation is provided in the P well, and the trench is filled with an insulating material 70.
A region 77 is a region other than the element isolating region at a main surface of P well 72, and a transistor is formed in region 77. A gate electrode 76 is provided on region 77. Impurity-doped region 80 serving as a source or a drain is provided on both sides of gate electrode 76. FIG. 30 shows a portion where an N channel MOS transistor is formed and, in this case, impurity-doped region 80 is implanted with an impurity of an N type.
Meanwhile, a region, where a transistor is not formed, in a portion other than the element isolating region is a dummy field 84, and this field is also usually implanted with an impurity of the same conductivity type as the source/drain region of an adjacent transistor.
The source/drain region of each transistor is connected to a first metal interconnection layer 88 through a contact hole. A second metal interconnection layer 90 is formed on first metal interconnection layer 88 with an insulating layer interposed therebetween.
FIG. 31 shows a typical layout of a semiconductor memory device.
Referring to FIG. 31, the semiconductor memory device includes memory blocks MBn arranged in two rows and two columns on semiconductor substrate 500. In a region CRS formed along a line segment connecting the middle points of the shorter sides of rectangular semiconductor substrate 500 and between memory blocks MBn, a power supply circuit IPS for generating an internal power supply potential, a terminal and input/output circuit DI for inputting/outputting data, a PLL circuit PL for generating clocks, a clock buffer CKB for distributing the clocks to each memory block and a control circuit, for example, and an address input buffer ABUF are provided. Further, a control circuit CC is provided at the center of the semiconductor substrate.
Since transistors are regularly and densely arranged in memory blocks MBn in such a semiconductor memory device, the above described dummy fields are rarely required. In the semiconductor memory device, the dummy fields are provided in regions other than the memory blocks, that is, region CRS formed along a line segment connecting the middle points of the shorter sides of semiconductor substrate 500 and between the memory blocks, a region CRL formed along a line segment connecting the middle points of the longer sides of semiconductor substrate 500 and between the memory blocks, and the outer peripheral portion of semiconductor substrate 500 in FIG. 31. Hereinafter, these regions are referred to as a periphery region.
Conventional dummy fields were arranged only for the purpose of precisely shaping the form of a transistor formation portion. Therefore, the dummy field themselves were not electrically connected to the first metal interconnection as shown in FIG. 30 and they were floating nodes. Thus, any design merits were not found.